Foreword
For the newbies
When you start delving into (yeah, I know this is a AI indicator phrase - by I wrote it myself) electronic circuit design this is most likely one of the things you'd encounter rather soon
There is a comparator with a push-pull output generating either a positive voltage Vp or a negative Voltage Vn. This voltage again charges / discharges a capacitor until the capacitor voltage hits a threshold which is a fraction of the output voltage (a.k.a. hysteresis). There are several names for this arrangement like "astable multivibrator" and "RC oscillator" and there is a somewhat more sophisticated version where the capacitor is replaced with an active integrator.
This circuit doesn't only generate a square wave but also a triangle wave and as I already pointed out [1] by adding one resistor the circuit starts acting as a PWM modulator. In this context some DTU people coined the term "astable integrating multivibrator (AIM)" and Stefan Wehmeier opted for calling it "self oscillating digital feedback amplifier (SODFA)" even if it is very far from being digital.
For the veterans
A lot of people are convinced that comparator and switching stage can be seen as a unit called 'power comparator' [MEY06a] and demand it to be as fast as possible in order to improve linearity (remember that!). Stefan Wehmeier is one of them - which he unmistakably documented elsewhere [2].
For the switching stage itself this guiding principle is perfectly fine as slow transistors require more dead time in order to stay cool which again creates more distortion for which you will need more loopgain to compensate for. However, fast comparators such as the LT1713 mentioned by Wehmeier tend to be pretty good 'HF junk to NF noise converters' - which is probably not what you want in the first place.
Well, wait a second. What was that? Instead of spending money on fancy wide bandgap switches [3] one could simply use an opamp and a few passives for increasing loopgain in order to get low distortion... Sounds cool? Yes, but increased loopgain tends to make the Class-D loop unstable.
About methods
The brute force method
Put your circuit in a simulator and see what happens. The problem with that: optimization can only be done manually and will be a very cumbersome process because you will start multiple simulations (e.g. one for distortion, one for clipping behavior, etc.) per parametrization just to judge the result by eyeballing.
The universal method
Bruno claims to have found a mathematical model that takes into account the sampling nature of a Class-D loop (the SMPA is only sensitive for 'changes within the loop' during the switching process of the comparator) and therefore precisely predicts what happens. However, he wants to keep this as a trade secret [5].
His work is based on the findings presented in [RIS05] of which he says that he did not understand the math in the first place [4]. Personally I guess that I still haven't understood yet.
But I do have a guess:
- Lars directly figured out that his comparator model 'just' works around 50% duty cycle. There it allows for finding the comparator gain as a function of frequency which perfectly matches the measured response using a bode analyzer. Obviously this is a huge step forward considering that until then the best approximation was a constant factor to be found by treating the comparator input as an independent signal [PUZ05].
- Look at the picture above called 'Figure 6' I took from his paper. Here he shows the waveforms of the 'clampled integrator comparator model' which is the basis for his further analysis. From the carrier c(t) he derives one slope factor.
- Now my first guess is that his model works because of the implicit assumption that the slope at the subsequent zero crossing of the carrier ('falling edge') is identical.
- And my second guess is that this is only true at 50% duty cycle. Look at the picture below called 'Figure 7' I took from [PUZ09] which depicts a carrier residual at 30%. The green line is clearly steeper than the red one.
The free method
So (unfortunately) the only thing that is left is the method / model Bruno disclosed in [PUZ09]. First of all he comes up with this:
There is an input, a feedback from the output, a LTI function H(s) and a power comparator. He states:
"
A self-oscillating amplifier is essentially a square wave oscillator constructed as a comparator with a linear function wrapped around it.
"
Believe me or not - there is a shitload of wisdom in these words! This is it. This is the archetype of an SMPA (I promised to come up with that [1])! Want to clock it? No problem, it's just another input [KEM12]. PSC? HC? No problem. One model fits all.
"In a self-oscillating amplifier, frequency f and duty cycle h are dependent. A given combination of duty cycle and frequency is an oscillation condition if there exists a voltage V0 that, when compared against the output of the loop function driven by a square wave of said frequency and duty cycle, produces another identical square wave"
This already smells like an algorithm! Choose h, vary f and at some point the two square waves perfectly match. Still, executing that algorithm sounds like a lot of work. But the good thing is that it can be rewritten as a mathematical statement. For that he first provides us with Fourier series representation of a square wave that has
- an amplitude of 1 and -1
- a dutycycle h between 0 and 1
- a frequency f
- a first rising edge at t=0
- a first falling edge at t=h/f
But wait, there is a problem. I did the math and can tell you that the sum starts at 1. Why is that? Starting with the inital cn-definition the sum runs from -inf to +inf. He then splits this sum into three parts:
- the 'negative half' of the sum from -inf til -1
- the 'positive half' of the sum from 1 til +inf
- the DC coefficient c0
- which turns out to equal 2h-1
However, at the point where he finally derives the oscillation criterion everything is fine and the sum starts at 1:
Bruno further points out that an equivalent expression looks like this:
Practical implementation
So, what do we need to actually work with that?
First of all we need to realize several things:
- The 'Laplace s' is defined as s = i · ω = 2i · π · f
- so the term H(2i · π · f · n) is another way of writing H(s · n)
- There is no need to calculate the sum until +inf as there is not much energy (information) in the higher harmonics
- Let's assume that the switching frequency to be found between 1 kHz and 500 kHz and that stopping the summation after 100 terms is sufficient. Then we need to know H(s) up to 50 MHz.
- When running an .ac simulation in LTspice it is possible to extract H(s) in a usable format into a text file by selecting the waveform window, clicking File -> Export and choosing "Cartesian: re,im" from the format drop-down menue
- The appropriate simulation statement would be: .ac lin 65535 1k 50meg
Here you can find the LTSpice file and H(s) output for the 'Fig. 2' example circuit in [PUZ09]:
Some years ago I put together a two step approach of dealing with this:
- first I manually stripped the text file to plain CSV
- second this was loaded into octave where a script did all the calculations
- as LTspice can only output 65535 frequency points everything is interpolated to 20 Hz steps
- create a duty cycle vector holding suitably spaced values between 0.05 and 0.95 or so
- calculate the left portion of the equation above in order to retrieve one phase plot per element in the duty cycle vector
- search for zero crossings in phase to determine the switching frequency per duty cycle
But wait, there's more!
About optimization
What optimization?
- The output LC filter (15ish µH and 2ish µF is usually a good choice)
- The feedback network (where one sets the overall gain and eventually adjusts the overall frequency response)
- The propagation delay of comparator, driver and power stage (which is just there)
- Minor contributors (such as a summing amplifier adding another pole at higher frequencies in order to fine-tune the switching frequency)
For reference
