Preface

The much I love tubes the more I prefer my amplifiers to be linear. So for over a decade I felt the urge to build a nixie clock - but I needed a little trigger to get the ball rolling.
Some years ago a friend of mine told me that he saw a video online and fell in love with nixies. He asked me whether I know about them - at a time when I was pregnant with the idea of building a nixie clock for quite a while. We talked to another friend of us who also loves the idea of some 'vintage, early cold war days'-energy wafting through his living room. As he is experienced in working with sheet metal we made a deal that he is going to design and build a nice stainless steel enclosure.

Yes, this is the n-th nixie-clock project on the internet. However, it might be somehow interesting because it does not use parts made from unobtainium and uses a little trick in the HV-supply you might not have seen before.

Design Targets

The clock should be supplied with 5V via a mini-USB jack (MOLEX) so it is possible to use one of these ubiquitous USB chargers.
Each nixie 'lives' on a separate daughter-board. This makes it easy to replace a nixie or to build a clock with some other tube than the IN-14 we used.
Four IN-14 nixies (hour, minute) only. But it shold be easy to derive a 6-nixie motherboard from the original design.
No LEDs (we think that the nixies stand for themselves and must not be accompanied by some fancy semiconductor illumination).
No Arduino (it's pretty easy to get a running AVR µC on a cusom PCB)
No DCF77 - for the sake of simplicity

Electronics

Driving the nixies

It seems to be a common technique to drive the nixies using the 74141 chip or its soviet counterpart. And somehow it seems to be harder to get one of these chips than some nixies. I guess that this is why some people try to build a clock using this chip only once - which leads to anode multiplexing:

Some people use HV-optocouplers for this purpose

https://www.microfarad.de/nixie-clock/

And some other people use transistors

https://www.instructables.com/id/Arduino-4-Tube-Multiplexed-Nixie-Clock/

My quesions is: if you are already fiddling around with some HV-BJTs why would you opt for wasting brightness by turning on each tube for only a fraction of a given time interval (in order to get the count of obsolete chips down) and not for avoiding obsolete parts in general and designing a proper nixie-driver using some more (cheap) BJTs?

The solution presented here uses one HV-BJT (e.g. BF820) in SOT23 per cathode. These transistors and a couple of resistors are directly placed on the nixie-daughterboard.

In addition there is a 10-bit latch per tube and all latches are driven from a single BCD-to-DEC (HEF4028) converter. So we need just 8 µC pins (4x latch enable and 4 BCD-lines) to drive four tubes. Everything is orchestrated by my favourite 8-bit µC: ATmega8 which is further equipped with a 32.768kHz XTAL and two microswitches to independently adjust hours and minutes.

About power

The HV supply runs directly from the 5V input whereas all the logic stuff runs from a regulated (MC...) 3V3 rail. Therefore every logic chip (ATMEGA8L, HEF4028, SN74LVC841) is specified for 3.3V operation.

HV Section

There are several options of how to convert a given DC voltage (5V) into a higher voltage (170V). The most well-known might be the boost converter and flyback converter. Both have some drawbacks:

The biggest drawback of the boost converter is that it's duty-cycle is directly linked to the ration of input to output voltage. In this application we would end up well above 90%. Event if in the end it is no real deal-breaker it is definitely not convenient.
While the flyback converter does not suffer from the duty-cycle issue (as the winding ratio can be adjusted to the voltage ratio) voltage stress in the components is higher as when either the transistor or diode blocks it 'sees' the reflected voltage from 'the other side' on top of the voltage from the 'own side'. Also the current stress for the components gets higher.

So I wanted to try something else. There is a less-known hybrid form of both converters, where the inductor is uses as a 'tapped' inductor - just as in an autotransformer. Only a part of the windings are used to store energy but the full amount of windings is used to discharge the inductor.

Here you can find a little (LTSpice) simulation showing the three topologies exemplarily doing the same job: stepping 10V / 2A up to 20V / 1A. Switching frequency is identical for all converters but component values are adjusted to achieve CrCM (transistor turns on again in the very moment the core is completely demagnetized) in each case.

Theoretically it would make sense to use thicker wire for the 'primary' or 'charging' winding - but that would have been a custom choke. Without that a fancy Coilcraft LPH8045 is going to do the job. The cool thing about the 1:1:1 winding scheme is that is allows for an effective 1:3 catio in the HV supply which brings the duty-cycle well below 50% which again allows to use a cheap and simple UCC3805 without the need for slope compensation or other nasty tricks. Almost. Because this chip needs 1V on the CS-pin which is a lot of voltage drop over a shunt resistor in the transistor's source path when you only have 5V available. So I decided to throw in an INA10A1 to compensate for that.

Finally you will find a simulation of the entire HV section here.

Schematics

Manufacturing Data

Here are links to everything necessary for creating a copy of the project:

Excel spreadsheet

Gerbers

Assembly prints (2:1 / bottom mirrored / pdf)

Schematic prints (pdf)

3D data

step file of the complete assembly

Issues

There are two known issues with the design that were not fixed in the manufacturing data:

issue: unfortunately I messed up the pin mapping of the Coilcraft LPD inductor

fix: if you do not assemble it as shown in the 3D screenshot above (the silk layer does not contain any mounting info anyway) but as in the photo shown below everything is correct

issue: C15 needs way more capacitance than shown in the SCM / BOM (this is why the respective line of the BOM is highlighted)

fix: as replacement it is possible (also see photo below) to solder 2x 47µF 16V X5R caps in parallel (e.g.: 1210YD476MAT2A)

Software

The software of the project is super simple. Yes, I'm aware that an ESP32 board is dirt cheap and might get the time via NTP an what not. But this really is not my piece of cake. So everything can be found in one file. Sorry, but the variable names are crap - "uos" means "units of seconds" and so on.

I used ATMEL-Studio 6 (or 7 I don't remember exactly) and compiled it into a little binary that I flashed onto the controller using this adapter.

I'm still in love with this mesmerizing effect:

Housing

Well, I guess that is a real shortcoming of the project. As I'm not a mechanical guy at all I cannot provide you with any details about the housing at all. It exists and it somehow fits. This is all I know. However, as I had not foreseen any means for fixation on the PCB itself I simply glued everything into the housing which doesn't have a bottom cover.

While the electronics can be built 'as is' and the software can be used 'as is' this topic certainly needs some skills and creativity...

Cheers,

Foreword

Let's start this thing with a look into linear amps. In order to increase the efficiency of Class-AB amps it's a common practice to modulate the rail voltage of the output stage transistors so to minimize their Vce. As Bob pointed out in chapter 5.6 of his book [1] there is some conflicting terminology - because it's also the way I learned it I'll use Bob's way of naming things.

Class-H

In case these modulation happens step-wise the concept is called Class-H. Although there were many designs out there none of them did something spectacular. The only implementation that stood out a little was the 'VZ'-design by Crown which did not only change the voltage but also the impedance of the supply.

Class-G

In case the modulation is done in a continuous fashion the topology is called Class-G. For sure, the most straightforward way to do this is to put even more BJTs into the box (see below). But the smarter way of course is to use a buck regulator. And of that there were three implementations we're going to discuss briefly.

Lab.Gruppen

They used a plain and simple clocked (614kHz) buck converter with PI controller in their FP series amplifiers [2]. Nothing spectacular but apparently they were quite successful with that.

Yamaha

These guys had a quite innovative idea - they kept the Class-G BJT stage but sensed its collector current [green parts]. When a certain threshold is exceeded another transistor is switched on that then feeds via an inductor [orage parts] current into the common node between Class-G stage (emitter) and output stage (collector) [blue]. Once the sensed current fell below the threshold a gate discharge circuit caused the FET to turn off fast.

This is nothing more than a self-oscillating, hysteretic current-mode buck-converter with linear ripple eater. Isn't that beautiful compared to the Lab.Gruppen design? (Think about "technical minimal systems"... [3]).

Philips

Then again there were people at Philips [sic!] who did this [4]:

Wait a second isn't that a UcD? Yes, it is - two unipolar ones. In 1985! The patent spec. states:

So Bruno Putzeys did not invent the UcD [5]? Well, I guess he did - but at the time he was struck by enlightenment the novelty was already gone.

Nowadays he is fully aware of that - maybe because a swede came across his way...

Once upon a time

I searched the internet. I don't exactly remember what I entered into the google search bar but this URL was part of page three (back in the day when there was no AI one sign of true desperation was feeling the urge to open page 2 ff. of google results):

https://tc.prv.se/aktinsyn/servlet/singlepdf/?ansnr=09502956&ordnr=52&lang=en&sort=

Sounds like a thriller, right? So I had a look at the URL and asked myself what would happen if I changed the parameter ordnr=xx. Well, it appears that there are even more exciting documents! Here are the most relevant ones:

At the time I initially stumbled over this I downloaded all the files manually. Nowadays things are easier so I vibe-coded a little python script that does the job for you (if you want) and also gives the files some meaningful names. download

Lingua franca

Unfortunately, I do not understand Swedish. But apparently the link to German is so short that it was no big deal for me to grasp at least some parts of the last document. Apparently section 1.4.1 tells us, that the UcD was invented in the '70s by Clayton S. Sturgeon [6].

A vibe-translation looks as follows:

Now the very interesting part is, that in one of his most recent interviews [7] Bruno actually refers to that - maybe with a grain of salt - by stating:

But I guess at least it's some sort of achievement to be seen as a competitor by Bruno :-P

4041411 - the number of the beast

The basis for the UcD comes on two pillars:

in order to obtain a load independent frequency response and minimal output impedance the feedback of an amplifier circuit must be taken from the output (also knows as 'global feedback'). However, in case of an SMPA the LC filter is inbetween...
This filter comes with two state variables (inductor current and capacitor voltage) and in order to get a stable system both must be fed back (at least partially over frequency)

Inductor current

In SMPS design it's common practice to nest a current control loop inside a voltage loop in order to 'solve' the 'feedback from behind the filter'-problem.
In 1999 Dave Edwards (analogspiceman) adapted this method for SMPA which is also known as "Leapfrog" method [8].
Another well-known implementation is the BPCM from Høyerby [HOY05].
However, the big problem here in general is that the inductor current also carries the output current of the amplifier - something that doesn't need to be fed back - just 'the ripple' is of interest. Also Edwards (at least kind of) figured out that the capacitor current could be the perfect 'replacement' as it covers the ripple but not the load current.

Capacitor current

To my knowledge there is only one implementation that really sensed the capacitor current - which is the mueta-amp [HUL02]. All other implementations also use the capacitor current - but in a smarter way.

Capacitor current estimation

Have a look at the unipolar UcD again. The capacitor in the lead-lag network does nothing less than 'estimating' the current in the LC-filter capacitor where R17/R18 act as the 'shunt' resistance for converting the current into a voltage. The resistor in series with the capacitor helps in minimizing the frequency range of the estimation.
Without that resistor we end up at the GLIM amplifier [POU04a].

How to improve the UcD?

The plain UCD comes with two 'issues' that will be individually covered in the following sections.

Closed loop frequency response

It's fairly easy to see that the closed loop response of the UcD is that of a first order low-pass. It would be desirable to keep amplitude and phase more stable across the (upper) audio band by turning it into a second order function.

One way to achieve this is to split up the feedback resistor and insert a capacitor to ground (or to the 'mirror node' in a balanced design).

For the design of the 'Eigentakt'-loop Bruno came up with another concept (using some more parts but giving a better controllable result) I'll cover in another post.

Increased loopgain

Please note: this post does not deal with clamping techniques as I'm convinced that this is the rather trivial part.

The UcD already gives a decent amount of loopgain (especially at the upper end of the audio range). However, it always makes sense to ask for more. How is it done? By nesting the UcD inside another feedback loop.

However, this again creates two dynamic nightmares:

Fist, the control loop does not 'know' about the first order behavior of the UcD so it will try to flatten it out - which doesn't make too much sense
Second, as the UcD is a quite linear device in itself the output of R(s) must not only carry the error correction signal but also the input signal

Both issues can be solved in several different ways:

Textbook method #1 (Hypex Ncore)

It's quite easy to see that the loop filter can be relieved of the task of providing the foll input signal at its output simply by additively feeding in (feed-forward) said input signal behind the filter. In a further step the input signal might be split into two paths

one still being the feed-forward path
the other being pre-filtered with a filter mimicking the closed-loop transfer function of the UcD

In general this scheme is well known in standard control theory "conditional feedback" / "Führungsgrößenfilter mit Vorsteuerung" [9], [10 : chapter 5.3.1] but most likely Bruno was the first one who adopted this scheme for SMPAs [PUZ09].

The cool thing is that this can be done easily in a fully differential manner [11 : page 16] (which is definitely what you want when designing a high-power SMPA [PUZ13]) without any additional OpAmps (except the one for the loop filter).

Textbook method #2

Let's think about error correction [V&L79] for a moment.

Obviously the red node carries the error signal. Which is not exactly true in our case as it also contains the inevitable upper&above audio-band roll-off of the actual amp. Pre-filtering the input signal again helps here (green).

This structure is a special case of the "Internal Model Control" (IMC) shown in [10 : chapter 5.3.2] - and the open question is how to shape the error term over frequency such that a desired loopgain function exists. I'll cover that in another post.

Patrik's method #1 ("Adaptive Modulation Servo" [AMS])

The idea is to take the error signal from the inverting comparator input, inversely amplify it and feed the result into the non-inverting comparator input [12]. This comes with a good and a very bad aspect:

Good: while in the aforementioned approaches the complexity of K'(s) goes up when designing K(s) with a non-1st-order closed loop response here this doesn't happen - simply because there is no (explicit) K'(s)-function involved. Still, the control loop doesn't 'try' to flatten change the frequency response of the actual SMPA.
Bad: this method only works with a single-ended circuit (which definitely is not what you want when designing a high power SMPA).

I guess this is why he wrote [13]:

Patrik's method #2 ("OP1 loop")

Here the first stage of the self osc. loop is an OPAMP which senses the input and output of the SMPA differentially. Form an IMD-perspective this is clearly not the best solution so carefully selecting OP1 is a must. Possible part choices are:

AD8066
OPA627
OP1 in the ICEedge chipset
...

After OP1 the signal is split into (at least) to paths:

a lo-gain path that directly arrives at the comparator input
a hi-gain path that further amplifies the error signal and comes with additional clamping

Overall this kind of works like the AMS but the design can be made differential in all places where it really matters [14]. And yes, it is possible to build quite decent SMPAs with that (in this case also including a medium-gain path):