Class-D Tales: From Unitiy 'til Infinity (which for practical reasons might be approximated as 101)

Foreword

For the newbies

When you start delving into (yeah, I know this is a AI indicator phrase - by I wrote it myself) electronic circuit design this is most likely one of the things you'd encounter rather soon

There is a comparator with a push-pull output generating either a positive voltage Vp or a negative Voltage Vn. This voltage again charges / discharges a capacitor until the capacitor voltage hits a threshold which is a fraction of the output voltage (a.k.a. hysteresis). There are several names for this arrangement like "astable multivibrator" and "RC oscillator" and there is a somewhat more sophisticated version where the capacitor is replaced with an active integrator.

This circuit doesn't only generate a square wave but also a triangle wave and as I already pointed out [1] by adding one resistor the circuit starts acting as a PWM modulator. In this context some DTU people coined the term "astable integrating multivibrator (AIM)" and Stefan Wehmeier opted for calling it "self oscillating digital feedback amplifier (SODFA)" even if it is very far from being digital.

As the input voltage is varied the dutycycle follows proportionally. But the frequency of the pulsetrain doesn't remain constant. However, for this circuit it is possible to find the relationship between switching frequency and modulation index (which is another way of expressing the duty cycle) symbolically as can be seen here (sorry for german / I stripped this from a larger document so this is why it looks a bit weird).

Unfortunately, for other circuits it's not possible to perform such easy symbolic analysis.

Remark: related terms are (among others): "bang bang control", "sliding mode control", etc.

For the veterans

A lot of people are convinced that comparator and switching stage can be seen as a unit called 'power comparator' [MEY06a] and demand it to be as fast as possible in order to improve linearity (remember that!). Stefan Wehmeier is one of them - which he unmistakably documented elsewhere [2].

For the switching stage itself this guiding principle is perfectly fine as slow transistors require more dead time in order to stay cool which again creates more distortion for which you will need more loopgain to compensate for. However, fast comparators such as the LT1713 mentioned by Wehmeier tend to be pretty good 'HF junk to NF noise converters' - which is probably not what you want in the first place.

Well, wait a second. What was that? Instead of spending money on fancy wide bandgap switches [3] one could simply use an opamp and a few passives for increasing loopgain in order to get low distortion... Sounds cool? Yes, but increased loopgain tends to make the Class-D loop unstable.

Wait again. It was said that a (self-osc.) Class-D loop cannot go unstable as it already oscillates [4]. The thing here is that when a linear amplifier goes unstable it starts oscillating. Instability in a Class-D loop means that it switches at an undesired frequency. Which could lead to thermal destruction.

About methods

Obviously it would be nice if one could predict the behavior of such loop. And there are three methods of doing so.

The brute force method

Put your circuit in a simulator and see what happens. The problem with that: optimization can only be done manually and will be a very cumbersome process because you will start multiple simulations (e.g. one for distortion, one for clipping behavior, etc.) per parametrization just to judge the result by eyeballing.

The universal method

Bruno claims to have found a mathematical model that takes into account the sampling nature of a Class-D loop (the SMPA is only sensitive for 'changes within the loop' during the switching process of the comparator) and therefore precisely predicts what happens. However, he wants to keep this as a trade secret [5]. 

His work is based on the findings presented in [RIS05] of which he says that he did not understand the math in the first place [4]. Personally I guess that I still haven't understood yet.

But I do have a guess:

• Lars directly figured out that his comparator model 'just' works around 50% duty cycle. There it allows for finding the comparator gain as a function of frequency which perfectly matches the measured response using a bode analyzer. Obviously this is a huge step forward considering that until then the best approximation was a constant factor to be found by treating the comparator input as an independent signal [PUZ05].  

• Look at the picture above called 'Figure 6' I took from his paper. Here he shows the waveforms of the 'clampled integrator comparator model' which is the basis for his further analysis. From the carrier c(t) he derives one slope factor.

• Now my first guess is that his model works because of the implicit assumption that the slope at the subsequent zero crossing of the carrier ('falling edge') is identical.

• And my second guess is that this is only true at 50% duty cycle. Look at the picture below called 'Figure 7' I took from [PUZ09] which depicts a carrier residual at 30%. The green line is clearly steeper than the red one. 

Apparently Bruno found a way to extend Lars' model at exactly this point...

The free method

So (unfortunately) the only thing that is left is the method / model Bruno disclosed in [PUZ09]. First of all he comes up with this:

There is an input, a feedback from the output, a LTI function H(s) and a power comparator. He states:

" 

A self-oscillating amplifier is essentially a square wave oscillator constructed as a comparator with a linear function wrapped around it. 

"

Believe me or not - there is a shitload of wisdom in these words! This is it. This is the archetype of an SMPA (I promised to come up with that [1])! Want to clock it? No problem, it's just another input [KEM12]. PSC? HC? No problem. One model fits all.

Subsequently, he starts building a criterion for the oscillation condition - referring to the figure above where I added my red and green lines:

" 

In a self-oscillating amplifier, frequency f and duty cycle h are dependent. A given combination of duty cycle and frequency is an oscillation condition if there exists a voltage V0 that, when compared against the output of the loop function driven by a square wave of said frequency and duty cycle, produces another identical square wave 

"

This already smells like an algorithm! Choose h, vary f and at some point the two square waves perfectly match. Still, executing that algorithm sounds like a lot of work. But the good thing is that it can be rewritten as a mathematical statement. For that he first provides us with Fourier series representation of a square wave that has 

• an amplitude of 1 and -1 
• a dutycycle h between 0 and 1 
• a frequency f 
• a first rising edge at t=0
• a first falling edge at t=h/f

But wait, there is a problem. I did the math and can tell you that the sum starts at 1. Why is that? Starting with the inital cn-definition the sum runs from -inf to +inf. He then splits this sum into three parts:

• the 'negative half' of the sum from -inf til -1
• the 'positive half' of the sum from 1 til +inf
• the DC coefficient c0
• which turns out to equal 2h-1

 

Further inspection reveals that the lower half of the sum just equals the complex conjugate of the upper half of the sum. This means that the result of the addition equals two time the real part of one half of the sum of which it is more convenient to use the positive one - which starts at 1.

However, at the point where he finally derives the oscillation criterion everything is fine and the sum starts at 1: 

Bruno further points out that an equivalent expression looks like this:

Practical implementation

So, what do we need to actually work with that?

First of all we need to realize several things:

• The 'Laplace s' is defined as s = i · ω = 2i · π · f

• so the term H(2i · π · f · n) is another way of writing H(s · n)

• There is no need to calculate the sum until +inf as there is not much energy (information) in the higher harmonics

• Let's assume that the switching frequency to be found between 1 kHz and 500 kHz and that stopping the summation after 100 terms is sufficient. Then we need to know H(s) up to 50 MHz.

• When running an .ac simulation in LTspice it is possible to extract H(s) in a usable format into a text file by selecting the waveform window, clicking File -> Export and choosing "Cartesian: re,im" from the format drop-down menue

• The appropriate simulation statement would be: .ac lin 65535 1k 50meg

Here you can find the LTSpice file and H(s) output for the 'Fig. 2' example circuit in [PUZ09]:

Some years ago I put together a two step approach of dealing with this:

• first I manually stripped the text file to plain CSV
• second this was loaded into octave where a script did all the calculations
• as LTspice can only output 65535 frequency points everything is interpolated to 20 Hz steps
• create a duty cycle vector holding suitably spaced values between 0.05 and 0.95 or so
• calculate the left portion of the equation above in order to retrieve one phase plot per element in the duty cycle vector
• search for zero crossings in phase to determine the switching frequency per duty cycle

But wait, there's more!

Combing back to "Figure 7" which I used to draw the green and red line you will notice that there is an offset between V0 and the average of Vmod which is the effective DC at the comparator input. It is further shown in the paper that this can be calculated by evaluating the following expression:

The evaluation now works by inserting known combinations of f and h and calculating the sum accordingly. However, it should again start at 1. By calculating the derivative of this DC input term it is possible to obtain the actual DC gain of the modulator - which is basically nothing less than its linearity. Apparently, this linearity is 'just' a function of H(s). Chew on that for a while!

As I wanted to practice my vibe coding skills I used an LLM to combine the two steps into one python script together with some improvements to the old octave thingy. It can be downloaded here.

About optimization

What optimization?

Well, what have we gained so far? It is possible to predict switching frequency and modulator linearity at once but the actual tuning of a circuit is still requires brute force action - i.e. running the script for several H(s). 

But this can be changed! Let's go back to the loop I presented in an earlier post [6]. 

This circuit can be split into a combination of a 'constant' Hc(s) and a parametric, tuneable Hp(s). The first (depicted in green) comprises components that are chosen due to criteria which are not (directly) linked to loopgain and modulator linearity - such as:

• The output LC filter (15ish µH and 2ish µF is usually a good choice)
• The feedback network (where one sets the overall gain and eventually adjusts the overall frequency response)
• The propagation delay of comparator, driver and power stage (which is just there)
• Minor contributors (such as a summing amplifier adding another pole at higher frequencies in order to fine-tune the switching frequency)

The latter comprises all other parts of the loop which are meant to increase the loopgain within the audio band. By expressing the transfer function of such (opamp) circuits in the Laplace domain it is rather simple to derive Hp(s) as a function of component values (or more abstract auxiliary values such as Q and f). By pre-fixing some of the components (e.g. the resistors shown in red) and limiting the values of other components to feasible ranges the complexity of the problem can be reduced.

Wait, which problem? Well, now it is possible to let a numerical optimization find these component values which (for example) result in the least possible deviation of the normalized DC-gain from unity.

That's it! Brute force is gone! However, I'll leave this part of the implementation as an exercise for the reader ;-)

For reference

Putting the NAD M22 loop [7] into the simulator yields the following result:

The normalized modulator gain stays around unitiy up to |m|=0.8 which means that the amplifier makes it well up to 0.64 times it's nominal output power until modulator distortion starts kicking in.

That's remarkable!

Cheers,

P.

Circuit Snippets: Currents In Amplifiers

Output Current Measurement

A lot of DIY projects are lacking features that are essential in commercial amplifier assemblies - such as output current measurement. In 'system amps' this is often required to implement advanced DSP stuff or speaker impedance measurement. Off the shelf modules targeted for such applications comprise imon output signals - such can be found e.g. in the ICEpower 1200AS module [1].

So how to do output current measurement?

In case it is guaranteed that the amplifier channel is not being bridged external (and if it is done internally a 'grounded bridge' configuration is chosen) a simple resistor connected to ground and in series with the load could do the job. But in case the amplifier is an SMPA you will end up in a little dilemma:

• It is a very clever idea to (differentially) take the actually self-oscillating feedback of the loop directly from the filter capacitor.
• It is a not so clever idea to place the shunt resistor in series to the capacitor

In Ncore-style loops you have the degree of freedom to tie the feedback takeoff for the inner UcD loop to the capacitor while sensing closely to the physical output of the assembly with the 'outer' loop. For all other loop arrangements the only method is to keep the resistor as small as possible in order not to compromise the output impedance of the amplifier.

Using a high-side shunt measurement seems to be tempting as it would allow for external bridging, however, the diff-amp will the the full output voltage swing as common mode and if there is only a very tiny bit of inequality in the resistors and/or a limited CMRR of the OP itself (which both cannot be avoided) the resolution (especially at higher load impedances [much voltage for less current]) of this 'measurement' is rather poor.

In my opinion using a hall sensor is clearly the easiest option.

Another solution can be found in the ICEpower 1200AS module (which features a ton more of super interesting concepts). The shunt resistor is hidden underneath the filter capacitor and the 'evaluation circuitry' is encircled in pink.

Here a high-side shunt is combined with a floating OP that senses the voltage drop and converts it into a current that is mirrored at V+ and then evaluated at GND potential. A similar circuit is sketched below However, this only works reliably if it is guaranteed that the output stays away from the rail with a margin of 3V or so. I'll cover this topic in another post.

In contrast Hypex modules often comprise a current measurement where the output current is 'estimated' by open-loop integration of the voltage of a 'secondary' winding on the filter inductor [2]. A concept I'd consider being flawed - which is why I'm not showing it here.

Output Over Current Detection

In case a simple 'overcurrent yes/no' information is sufficient things get even easier.

For decades there was a small manufacturer of affordable and reliable speakers and amps in Karlsruhe: KMT. Sadly, the owner Martin Meinzer passed away in 2023 and now the business is permanently closed. For some years they offered the S3000 amplifier which was (according to my knowledge) developed by Alexej Gerbershagen who now runs Lexa Audio.

While this device is highly interesting as a whole because it comprises a modified version of the Yamaha EEEngine topology [3] (with BJTs for switching and lateral FETs for the linear stage ;-) ) it also comes with a floating output over current detector:

The full schematic of the S3000 can be found here.

SMPA Switching Stage Protection

Cycle-bc-Cycle Current Limit: Introduction

The interesting thing about a SMPA power stage is that (together with the inevitable inductor of the LC filter) it can be made completely short circuit proof.

In switching regulators said behavior known as 'cycle-by-cycle current limit'. The idea behind is rather simple:

• Once the overcurrent is detected (fast measurement needed) the power stage is 'deactivated' which means that all gates are discharged. The current in the inductor will then further flow via the body diodes of the switching stage - such that it ramps towards 0A
• Ideally this is done using gate driver offering a fast enable/disable input such as the Si8244 [4] 
• I once had a conversation with a SiLabs representative. They confirmed that
• Si8244 is exactly identical to SI8234 (they just wrote 'Class-D' in the datasheet to attract different customers)
• The output sections are 'really' independent which means that the H-bridge can be connected 'the wrong way round' which gives some nice options in layouting
• In this situation the output voltage will no more follow the input voltage and therefore the voltage loop (which is hopefully closed behind the finter) goes into saturation
• Then
• Either after the current fell below the OVC threshold and a defined time interval (e.g. 2µs) has expired
• Or after the current fell below a second threshold
• The drive is activated again. Because of the saturated voltage loop the transistors will turn on such that the current ramps up again.
• In essence this means that the loop transitions from a voltage loop to a (more or less) hysteretic current loop while CbC-limit is active.

Here you see an amplifier driving a 8 Ohm load:

• The yellow-brown-ish trace shows the output voltage, the pre-clipper limits the excursion
• The blue trace shows the inductor current

Aganin the same amplifier and scope config but now with a 2 Ohm load:

Cycle-bc-Cycle Current Limit: Integrated Solutions

There are several gate driver ICs which directly embody this feature by measuring the voltage drop across Rds_on - which results in a very temperature dependent current limit behavior.

Taken from the IPT210N25NFD datasheet [5]

More sophisticated gate drivers adjust the internal threshold with a measured temperature (using a NTC) - which is very nice in case you use SMD transistors and the NTC is directly coupled to the drain tab. However, for high power designs there is still no way around TO247 or even larger packages - for which this solution will not work very well.

So in the end you will use simple resistors. Trust me ;-)

Cycle-bc-Cycle Current Limit:  Implementation Details

Full Bridge Circuit

In theory one sensing resistor is sufficient in a full bridge switching stage. However, when it comes to layout considerations it might make more sense to use two resistors and add up the sensed voltages (as shown in the sketch below). The signal is then amplified and fed to a comparator.

One thing needs to be considered:

• 'Standard amps' are often built in a way that the power stage is sized for a desired output voltage and then everything is made beefy enough to support 2 Ohm loads (at full voltage).
• When the load situation is known better (active speakers, system amps) it might be sufficient to make the amp able to support a given power rating (2kW in the case shown above) into 8 Ohms (voltage limited) and 4 Ohms (current limited).
• When there is a real short circuit the voltage on the output will be close to 0V when the current limitation kicks in. This means that when the transistors are turned on again the voltage across the inductor is large and therefore the current ramps up fast. Or in other terms: the oscillation frequency of the current loop will be high.
• When this amplifier now runs into overcurrent at 4 Ohms there is a comparatively substantial output voltage so the voltage across the inductor, current slope and switching frequency of the current loop will be less than in the example before.

-> Bandwidth of the amplification must be selected such that both cases result in equal limitation current. However, it seems to be possible to get decent results using cheap parts such as TLV9061 and AP331A.

In case the gate driver input side is GND referenced you might want to shift the signal 'upwards' using a digital isolator. It is further possible to bury some functional safety aspect in this circuit by using low active logic - e.g. using an (fast) optocoupler where the LED must be lit in order to enable the gate drivers.

The mentioned time delay is then most easily implemented at the output of the isolator using a RCD circuit and a schmitt-trigger input buffer/inverter.

Half Bridge Circuit

While the implementation was very straight forward for the full bridge in a half bridge circuit things start to become complex because you need two current measurements.

One solution (that can be found in Hypex modules [2]) is to place a shunt resistor in the drain path of the high-side FET and another one in the source path of the low-side FET. Both shunts are used to 'detune' current mirrors which then create an output current that is somewhat proportional the the current in the shunt. By rearranging the current mirror and feeding the upper one from its lower counterpart it is possible to end up with a circuit having just one output which can then again be handled by one comparator and RCD circuit.

A simulation of this circuit can be found here.

Shutting Off

Most likely the SMPA assembly cannot stay in CbC-limit forever due to thermal reasons. So after a while you would want to shut off the SMPA. This can be realized by counting the pulses in the enable signal e.g. using a µC by

• configuring a HW counter/timer to count the pulses
• read the counter value every 1 ms (+ reset to 0 afterwards)
• feed the value into a low pass filter
• compare the filter output against a threshold
• ideally the threshold is somewhat dependent on heat sink temperature
• shutting down the entire SMPA (channel) once the threshold is reached

Further Protective Measures

Maybe in hifi circles the myth that an amplifier should be able to generate output at its peak power for unlimited still lives on. But for professional applications it is common to build a SMPS that fully utilizes a B (or even C) breaker characteristic which allows the amp to generate several kilowatts for milliseconds to seconds. However, in the long run the available power from a 16A breaker is limited to something around 3600W. These might be distributed as follows:

• 200 W loss in the SMPS
• 100 W loss per SMPA channel
• this is what the cooling will be designed for
• 4x 750 W permanent SMPA output power
• which equals modest 14 Arms into 4 Ohms

Still it might make a lot of sense to design the cycle-by-cycle current limiter such that it act at +-90 Apk. So there is plenty of headroom for thermally overloading one SMPA channel in particular. Say we're running at 56 Arms (thereby not hitting the +-90 A limit) at 2 Ohms this means 6200W - which the SMPS will be able to deliver for a while. In a first approximation this would mean 1600 W loss in that channel instead of 100 W. The junction temperature of the FETs will be skyrocketing long before the thermal sensor on the heatsink will even notice it.

Smart people would now say: "let the DSP handle it". Yes and no.

In such complex systems of multiple assemblies it is a best-practice approach to design each sub-assembly in a way that it is able to fully protect is self (so you could torture it on a lab bench w/o it's companions).

Now imagine 

• you already implemented a hall sensor based current measurement circuit
• and there already is a µC (which also does the pulse counting as described above) 
• which allows for real-time processing but with a rather modest sampling rate of 1 kHz

so directly sampling the imon output is not an option. Instead (after stripping the DC offset from the hall sensor IC output) you'd want to rectify and average the signal. The circuit on the left is well known [6] as an implementation of a precision full-wave rectifier. It is easy to see that adding a single capacitor yields an RMS-estimator which can be seen on the right 

However, when you design this circuit for appropriate ripple reduction (e.g. at 20Hz) you will also get a rather slow settling to the correct output value. But by adding one more resistor and capacitor this circuit can be turned into a second order circuit giving way less response time w/o compromising ripple suppression:

A simulation of the circuit can be found here.

The output of the RMS-estimator can now be sampled using a µC and converted (e.g. by using a pre-computed lookup table) into a temperature difference between the heat sink temperature and the actual junction of the transistors. Adding said difference to the measured (e.g. using a NTC) heat sink temperature yields a junction temperature estimation. Implementing two shut off threshold temperatures (e.g. 85°C for the heat sink and 115°C for the junction) will ensure stable operation under all conditions.

Cheers,

P.